An issue has been identified in Arm C1-Pro before r1p2-50eac0, where, under certain conditions, a TLBI+DSB might fail to ensure the completion of memory accesses related to SME.
Exploitability
AV:LAC:HPR:LUI:NScope
S:UImpact
C:NI:LA:L3.6/CVSS:3.1/AV:L/AC:H/PR:L/UI:N/S:U/C:N/I:L/A:LConcurrency